Emerald Systems provides training classes to cater to the needs of MNCs, design houses, educational, institutions or to any party interested in IC Design. The industry-standard training classes are conducted by design engineers with many years of design experience.
Most of our training customers are from the industry, whereby we conduct custom-tailored training to meet the specific needs and requirements of the industry. We provide both private (where participants are only from the respective MNC or design house) and public training (where participation is open to all). Among the training courses that we provide are:
| COURSES | DURATION | PRE-REQUISITE |
|---|---|---|
| Digital/ASIC Design Methodology Overview | 2 Days | None |
| Introduction to Verilog | 3 Days | None |
| Introduction to VHDL | 3 Days | None |
| Training on HDL Desginer Series for Graphical Design | 2 Days | None |
| Training on Modelsim | 2 Days | Knowledge on VHDL/Verilog |
| Design for Fabrication Methodology Flow From Design to Fabrication | 1 Day | None |
| Intermediate Verilog Coding | 4 Days | Basic Verilog |
| Intermediate VHDL Coding | 4 Days | Basic VHDL |
| Training on Synthesis | 4 Days | Basic knowledge on VHDL/Verilog, design |
| Analog desig: hierarchical design, testbenching, SDL, back annotation, parasitics, timing, floorplanning, spice corners, power/area/speed | 4 Days | Basic knowledge on spice |
| Mixed signal design: schematic -> HDL code -> shcematic Merging digital and analog flows | 4 Days | Basic knowledge on spice, Verilog/VHDL |
| Overview of Analo/Mixed Signal Design Flow, basic analog flow, fronted flow, backend flow, technology, process, rule files. | 4 Days | Basic knowledge on spice |
| Intensive IC VLSI layout training: Process, layout editing, LVS, DRC | 6 Days | Basic knowledge on design and semiconductor physics |
| Intensive IC VLSI layout training on SDL | 5 Days | Basic knowledge on design and semiconductor physics |
| FPGA Implementatio: Synthesis and Verification of Design Implemented on FPGA | 2 Days | Basic knowledge on VHDL/Verilog |
| Static Timing Analysis and Formal Verification | 2 Days | Basic design knowledge |
| Deep submicron design | 1 Day | Basic knowledge on design and semiconductor physics |
| Architecture of Microprocessors | 1 Day | None |
| Advanced Behavioral Verilog Coding | 3 Days | Basic knowledge on Verilog |
Emerald Systems also provides training in collaboration with several other insitutions.
- Penang Skills Development Corporation (PSDC)
Note: Expenses for training provided under PSDC is claimable under HRDF.
