Mentor Graphics

- Design Capture (Design Architect IC)

- Simulation (ADVance MS, Mach TA, Eldo, Eldo RF, ADVance MS RF)

- Physical Layout (IC Station SDL, ICgraph Basic, ICassemble, HotPlot, AutoCells)

- Physical Verification (Calibre DRC, Calibre LVS, Calibre DESIGNrev, Calibre Interactive, Calibre RVE)

- Parasitic Extraction (Calibre xRC, Calibre xL, Calibre LVS)

- Litho Modeling (Calibre OPCverify, Calibre RET (OPC and PSM))

- Mask Data Preparation (Calibre MDP)

- Design for Manufacturing (Calibre YieldAnalyzer, Calibre YieldEnhancer YieldAssist)

- Design Creation (HDL Designer, HDL Author, HDL Detective, Debug Detective)

- Simulation (ModelSim SE, ModelSim PE)

- Synthesis (Precision Synthesis, Precision RTL Synthesis, LeonardoSpectrum)

- Assertion-Based Verification (Questa AFV, Questa SV, 0-In® Assertion Synthesis, 0-In Formal Verification, 0-In®

- Clock-Domain Crossing (CDC), 0-In® CheckerWare®)

- Testbench Automation (Questa AFV, Questa SV)

- Coverage-Driven Verification

- Digital Simulation (ModelSim® SE, ModelSim® LE, ModelSim® PE )

- Analog/Mixed-Signal Simulation (Advance MS, ADVance MS RF)

- Hardware/Software Co-Verification (Seamless, Seamless FPGA)

- ATPG & Compression (TestKompress, FastScan, DFTAdvisor, FlexTest)

- Memory Test (MBISTArchitect, MacroTest)

- Boundary Scan (BSDArchitect)

- Logic BIST (LBISTArchitect)

- Yield Learning and Diagnosis (YieldAssist)